View AND8353D_7823514.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2008 december, 2008 ? rev. 0 1 publication order number: and8353/d and8353/d implementing cost effective and robust power factor correction with the ncp1607 prepared by: alan finkel on semiconductor introduction the ncp1607 is a voltage mode power factor correction (pfc) controller designed to drive cost ? effective converters to meet input line harmonic regulations. the device operates in critical conduction mode (crm) for optimal performance in applications up to about 300 w. its voltage mode scheme enables it to obtain unity power factor without the need for a line sensing network. the output voltage is accurately controlled with a built in high precision error amplifier. the controller also implements a comprehensive array of safety features for robust designs. this application note describes the design and implementation of a 400 v, 100 w, crm boost pfc converter using the ncp1607. the converter exhibits high power factor, low standby power dissipation, high active mode efficiency, and a variety of protection features. the need for pfc most electronic ballasts and switching power supplies use a diode bridge rectifier and a bulk storage capacitor to produce a dc voltage from the utility ac line. this produces a non ? sinusoidal current draw and increases the demand on the power delivery infrastructure. government regulations and utility requirements often necessitate control over line current harmonic content. active pfc circuits have become the most popular way to meet these harmonic content requirements. they consist of inserting a pfc pre ? regulator between the rectifier bridge and the bulk capacitor (figure 1). the boost (or step ? up) converter is the most popular topology for active power factor correction. with the proper control, it can be made to produce a constant output voltage while maintaining a sinusoidal input current from the line. figure 1. active pfc stage with the ncp1607 rectifiers + ac line high frequency bypass capacitor ncp1607 pfc preconverter converter load + bulk storage capacitor basic operation of a crm boost converter for medium power (<300 w) applications, critical conduction mode (crm) is the preferred control method. critical conduction mode occurs at the boundary between discontinuous conduction mode (dcm) and continuous conduction mode (ccm). in crm, the next driver on time is initiated when the boost inductor current reaches zero. hence, crm combines the lower peak currents of ccm operation with the zero current switching of dcm operation. this control method causes the frequency to vary with the line input voltage and the output load. the operation and waveforms of a pfc boost converter are illustrated in figure 2. for detailed information on the operation of a crm boost converter for pfc applications, please refer to and8123 at www.onsemi.com. application note http://onsemi.com
and8353/d http://onsemi.com 2 figure 2. schematic and waveforms of an ideal crm boost converter diode bridge in + ? l diode bridge in + ? l + the power switch is on the power switch is off critical conduction mode: next current cycle starts as soon as the core is reset. coil current + with the power switch voltage being about zero, the input voltage is applied across the coil. the coil cur- rent linearly increases with a (v in /l) slope. the coil current flows through the diode. the coil voltage is (v out ? v in ) and the coil current linearly decays with a (v out ? v in )/l slope. i l v out v in v drain (v out ? v in )/l i l(peak) i l v in v drain v drain v in /l v out v in if next cycle does not start then v drain rings towards v in + features of the ncp1607 the ncp1607 offers an ideal controller for medium power crm boost pfc applications. a simple crm boost pre ? converter featuring the ncp1607 is shown in figure 3. figure 3. crm boost pfc stage featuring the ncp1607 + ac line emi filter 1 4 3 2 8 5 6 7 fb control ct cs gnd zcd drv + c bulk load (ballast, smps, etc.) ncp1607 v out r s c in r zcd r out1 r out2 c comp v cc c t v cc d boost l boost pin 1 (fb) senses the boost output voltage through the resistor divider formed by r out1 and r out2 . this pin is the input to an error amplifier, whose output is pin 2 (control). a combination of resistors and capacitors between pin 1 and pin 2 form a compensation network that limits the bandwidth of the converter. for high power factor, the bandwidth is generally below 20 hz. a capacitor connected to pin 3 (ct) sets the on time for a given control voltage. cs (pin 4) gives cycle by cycle over current protection. this is accomplished with an intern al comparator which compares the voltage generated by the switch current and r sense to an internal 0.5 v reference. pin 5 (zcd) senses the demagnetization of the boost inductor. the driver on time begins when the voltage at this pin rises above 2.1 v (typ) and then drops below 1.6 v (typ). a resistor in series with the zero current detection (zcd) winding limits the current into this pin. additionally, by pulling this pin to ground, the drive pulses are disabled and the controller is placed in a low current standby mode.
and8353/d http://onsemi.com 3 the ncp1607 features a powerful output driver on pin 7. this driver is capable of switching the gates of large mosfets in an efficient manner. the driver incorporates both active and passive pulldown circuitry to prevent the output from floating high when v cc is off. pin 8 (v cc ) powers the controller. when v cc is below the turn on level (v cc(on) , typically 11.8 v), the current consumption of the part is limited to < 40 a. this gives allows for fast startup times and reduced standby power losses. alternatively, v cc can also be directly supplied from another controller, such as the ncp1230. this approach can further improve standby power performance in a two stage smps system. open feedback loop protection the ncp1607 features comprehensive protection against open feedback loop conditions by implementing ovp, uvp, and floating pin protection (fpp). there are three conditions in which the feedback loop can be opened. 1. uvp protection: the connection from resistor r out1 to the fb pin is opened. r out2 pulls the fb pin down to ground. the uvp comparator detects a uvp fault and disables thus disabling the drive. 2. ovp protection: the connection from resistor r out2 to the fb pin is open. r out1 pulls the fb pin up to the output voltage. the esd diode clamps the fb voltage to 10 v and r out1 limits the current into the fb pin. the v eal clamp detects a static ovp fault and the drive is disabled. 3. fpp protection: the fb pin is floating. the internal pull down resistor, r fb , pulls the fb voltage down below the uvp threshold. the uvp comparator detects a uvp fault and disables the drive. uvp and ovp protect the system from low bulk voltages and rapid operating point changes respectively, while the fpp protects the system against floating feedback pin conditions. w ithout fpp, if a manufacturing error causes the feedback pin to float, the feedback voltage is dependent on the coupling within the system and the surrounding environment. the coupled feedback voltage may be within the regulation limits (i.e. above the uvp threshold, but below v ref ) and cause the controller to deliver excessive power. the result is that the output voltage rises until a component fails due to overvoltage stress. for detailed information on the operation of the ncp1607, please refer to ncp1607/d at www .onsemi.com. design procedure the design of a crm boost pfc circuit is discussed in many on semiconductor application notes (see table 1). this application note describes the design procedure for a 400 v, 100 w converter using the features of the ncp1607. a design aid that allows users to quickly determine component values is available at www.onsemi.com. table 1. and8123 power factor correction stages operating in critical conduction mode and8016 design of power factor correction circuits using the mc33260 and8154 ncp1230 90 w, universal input adapter power supply with active pfc hbd853 power factor correction handbook *additional resources for the design and understanding of crm boost pfc circuits available at www.onsemi.com.
and8353/d http://onsemi.com 4 design step 1: define the required boost parameters minimum ac line voltage vac ll 85 v ac maximum ac line voltage vac hl 265 v ac line frequency f line 47 ? 63 hz boost pfc output voltage v out 400 v maximum output voltage v out(ovp) 440 v boost output power p out 100 w minimum switching frequency f sw(min) 50 khz estimated efficiency 92 % design step 2: calculate the boost inductor the boost inductor is calculated with equation 1: (eq. 1) l vac 2 v out 2 vac v out p out f (min) 2 to ensure that the switching frequency exceeds the minimum frequency, the boost inductor is evaluated at both the minimum and maximum rms line voltage: ? l 465 h for vac ll ? l 408 h for vac hl a value of 400 h is selected. equation 2 is used to calculate the resultant minimum frequency at full load. (eq. 2) f sw vac 2 2 l p out 1 vac 2 v out f sw is equal to 58 khz at 85 v ac and 51 khz at 265 v ac . design step 3: size the ct capacitor the ct capacitor must be large enough to provide the maximum on time at low line and full power. the maximum on time is given by: (eq. 3) t on(max) 2 l p out vac ll 2 12.0 s however, delivering an on tiem that is too long causes the application to deliver excessive power and also reduces the control range at high line or light loads. the ct capacitor is best sized slightly larger then that calcultated by equation 4: (eq. 4) ct i charge t on(max) v ctmax 2 p out l i charge vac 2 v ctmax where i charge and v ctmax are found in the ncp1607 datasheet. to ensure that the controller is capable of delivering the maximum on time, use the maximum i charge and the minimum v ctmax in the calculations for ct. from the ncp1607 datasheet: ? v ctmax = 2.9 v (min) ? i charge = 297 a (max) ct is equal to 1.2 nf. a normalized value of 1.5 nf ( 10%) provides adequate. design step 4: determine the zcd turns ratio a winding taken off of the boost inductor providess the zero current detection (zcd) signal. when the switch is on, the zcd voltage is calculated using equation 5: (eq. 5) v zcd(on) v in n b :n zcd where v in is the instantaneous ac line voltage. when the switch is off, the zcd voltage is calculated using equation 6: (eq. 6) v zcd(off) v out v in n b :n zcd to activate the zero current detection comparators of the ncp1607 (see figure 5), the zcd turns ratio is sized such that at least v zcdh (2.1 v typ) is applied to the zcd pin during all operating conditions. the turns ratio is calculated using equation 7. (eq. 7) n b :n zcd v out vac hl 2 v zcdh 11 figure 4. voltage waveforms for zero current detection winding zcd drain v out v zcd(on) v zcd(off) drv v zcdh v zcdl v cl(neg)
and8353/d http://onsemi.com 5 figure 5. zcd winding and internal logic arrangement zcd + ? + + ? + v cl(pos) clamp shutdown demag v cl(neg) active clamp + ? + reset dominant latch r q s drive r s r zcd v dd v in n zcd q n b v sdl v zcdl v zcdh a turns ratio of 10 is selected for this design. r zcd is added between the zcd winding and pin 5 to limit the current into or out of the pin. this current must be low enough so as to not trigger the zcd shutdown feature. r zcd is calculated using equation 8: (eq. 8) r zcd
vac hl 2 i cl(neg) (n b :n zcd ) 15.0 k where i cl(neg) = 2.5 ma (from the ncp1607 datasheet) the value of r zcd and the small parasitic capacitance of the zcd pin determines when the zcd winding signal is detected and the next drive pulse begins. ideally r zcd turns on the drive at the drain voltage valley to minimize switching losses. the value of r zcd large cause minimum drain voltage switching is fournd experimentally. too large of a value creates a significant delay in detecting the zcd event. in this case, the controller operates in discontinuous conduction mode (dcm) and the power factor is reduced. if r zcd is too small, then the next driver on time starts when the voltage is high and switching efficiency is reduced. design step 5: set the fb, ovp, and uvp levels the low bandwidth of the pfc stage causes overshoots during transient loads or at startup. the ncp1607 incorporates an adjustable overvoltage protection (ovp) circuit to protect against overshoots. the ovp activation level is set by r out1 . a derivation in the ncp1607 datasheet results in equation 9: (eq. 9) v out(ovp) v out(ovp) r out1 i ovp where i ovp = 10 a. r out1 is calculated using equation 10: (eq. 10) r out1 v out(ovp) v out i ovp r out1 is equal to 4.0 m . r out2 is sized to maintain 2.5 v on the fb pin when vout is at the targeted level. the fpp feature introduces an error into the output voltage. the output voltage including the error casued by r fb (v out ) is calculated using equation 11. (eq. 11) v out v out r out1 v ref r fb v out 400 4m 2.5 4.7 m 402 v the error caused by r fb is compensated by adjusting r out2 . the parallel combination of r fb and r out2 form an equivalent resistor r eq that is calculated using equation 12. (eq. 12) r eq r out1 v ref v out v ref r eq 4m 2.5 400 2.5 25.16 k r eq is used to calculate r out2 . (eq. 13) r out2 r eq r fb r fb r eq r out2 25.16 k 4.7 m 4.7 m 25.16 k 25.29 k for this design, a 25.5 k resistor is used for r out2 . the compensated output voltage is calculated using equation 14. (eq. 14) v out v ref r out1 r out2 r ou t2 r out1 v ref r fb v out 2.5 4m 25.5 k 25.5 k 4m 2.5 4.7 m 397 v
and8353/d http://onsemi.com 6 when determining the maximum output voltage level, care must be exercised so as not to interfere with the natural line frequency ripple on the output capacitor. this ripple is caused by the averaging effect of the pfc stage: the current charging the bulk cap is sinusoidal and in phase with the input line, but the load current is not. the resultant ripple voltage is calculated using equation 15: (eq. 15) v ripple(pk pk) p out c bulk 2 f line v out where f line = 47 hz (worst case for ripple) a bulk capacitor value of 68 f results in a peak ? to ? peak ripple of 12.5 v. this corresponds to a peak output voltage of 406.25 v, which is below the peak output overvoltage level (440 v). the ncp1607 also incorporates undervoltage protection (uvp). under normal conditions, the boost output capacitor charges to the peak of the ac line. if it does not charge to some minimum voltage, the ncp1607 enters undervoltage protection. the voltage on the output that triggers a uvp fault is calculated using equation 16: (eq. 16) v out(uvp) r out1 r out2 r out2 v uvp 48 v v out(uvp) 4m 25.5 k 25.5 k 300 mv 48 v note that this feature also provides protection against open loop conditions in the feedback path. if pin 1 is inadvertently floating (perhaps due to a bad solder joint), the controller senses that v fb is low and responds by delivering maximum power. the output voltage increases and over stresses the components. the ncp1607 incorporates two features to protect the application if fb is floating. the internal pull ? down resistor, r fb , ensures that the fb pin is pulled low if it is floating. additionally, an internal timer adds a 180 s delay during startup prior to the first drive pulse. since the built in error amplifier normally pulls fb to v ref , the ncp1607 disables the error amplifier during this time (figure 6). if the v fb remains less than uvp (300 mv typ), the driver and the error amplifier remain disabled. the combination of r fb and the start timer protects the application if the feedback loop is open during startup. fb fb control uvp wait uvp wait v uvp v eah v eal v out v out v cc(off) v cc(on) v cc uvp fault is ?removed? figure 6. timing diagram showing uvp and recovery from uvp uvp v ref if the fb pin floats during operation, v fb begins decreasing from v ref . the rate of decrease depends on r fb and the fb pin parasitic capacitance. as v fb decreases, the control pin voltage the on time increase until v fb < v uvp . when the fb voltage drops below the uvp threshold, then the undervoltage fault will be entered. the situation is depicted in figure 7. figure 7. uvp operation if loop is opened after startup v cc(off) v cc(on) v out loop is opened v uvp v ea h v ea l uvp control fb v out v cc v ref
and8353/d http://onsemi.com 7 design step 6: size the power components the power components are properly sized for the current and voltages applied to them. the stresses are greatest at full load and low line. 1. the boost inductor, l (eq. 17) i l(peak) 2 2 p out vac ll 3.62 a (eq. 18) i l(rms) 2 p out 3 vac ll 1.48 a 2. the boost diode, d boost i d(rms) 4 3 2 2 p out vac ll v out 0.75 a (eq. 19) 3. the mosfet, q1 i m(rms) 2 3 p out vac ll (eq. 20) 1 8 2 vac ll 3 v out 1.27 a the mosfeta maximum voltage is equal to the v out overvoltage level (440 v for this example). if an 80% derating is used for the mosfet?s bv dss , a 550 v fet provides adequate margin. 4. the sense resistor, r s (eq. 21) r s v cs(limit) i peak 0.14 p rs i m(rms) 2 r s 0.22 w (eq. 22) v cs(limit) = 0.5 v (typ) 5. the bulk capacitor, c bulk 32 2 p out 2 9 vac ll v out 2 (i load(rms) ) 2 0.70 a (eq. 23) i c(rms) the bulk capacitor value is calculated in step 5 to give an acceptable ripple voltage that does not trigger the output over voltage protection. this value may need to be increased so that the rms current is within the capacitor?s ratings. the voltage rating of c bulk is greater than the maximum v out level. since this design has an output overvoltage level of 440 v, a 450 v capacitor is selected. design step 7: supply v cc generally, a resistor connected between the ac input and pin 8 charges up the v cc cap to the v cc(on) level. because of the very low consumption of the ncp1607 during this stage, most of the current goes directly to charging up the v cc capacitor. this provides faster startup times and reduced standby power dissipation. the startup time is approximated with the following equation: (eq. 24) t start c vcc v cc(on) vac 2 r start i cc(startup) where i cc(startup) = 40 a (max) when the v cc voltage exceeds the v cc(on) level (12 v typical), the internal references and logic of the ncp1607 turn on. the controller has an undervoltage lockout (uvlo) feature that keeps the part active until v cc drops below about 9.5 v. this hysteresis allows ample time for another supply to take over and provide the necessary power to v cc . the zcd winding is an excellent candidate, but the voltage generated on the winding can be well below the desired v cc level. therefore, a small charge pump must be constructed to supply v cc . such a schematic is illustrated in figure 8. figure 8. the zcd winding can supply v cc through a charge pump circuit + 1 4 3 2 8 5 6 7 fb control ct cs gnd zcd drv ncp1607 c in v cc r start d 1 d 2 i aux c 1 r 1 r zcd c vcc + l boost c1 stores the energy for the charge pump. r1 limits the current by reducing the rate of voltage change. d1 supplies current to c1 when its cathode is negative. when its cathode is positive it limits the maximum voltage applied to v cc . when the zcd winding is switching, the voltage change across c1 over one period is: (eq. 25) v c1 v out v cc n b :n zcd therefore, the current available for charging v cc is: (eq. 26) i aux c1 f sw v c1 c1 f sw v out v cc n b :n zcd for off line ac ? dc applications which require pfc, a 2 stage approach is generally used. the first stage is the crm boost pfc. this supplies the 2nd stage ?? traditionally an isolated flyback or forward converter. this solution exhibit excellent performance at a low cost. however, during light load operations, the input current is low and the pfc stage is not necessary. in fact, leaving it on only degrades the efficiency of the system. advanced controllers, such as the ncp1230 and ncp1381, detect this light load case and instruct the pfc to shut down (figure 9). the ncp1607 is compatible with this type of topology, provided that the supplied v cc is initially greater than the ncp1607?s v cc(on) level.
and8353/d http://onsemi.com 8 figure 9. using the smps controller to supply power to the ncp1607 1 7 6 5 2 3 4 ncp1607 + + + + 1 7 6 5 2 3 4 ncp1230 88 v cc + c bulk d boost pfc_v cc design step 8: limit the inrush current the sudden application of the mains to the pfc converter causes the circuit to experience an inrush current and a resonant voltage overshoot that is several times normal values. to resize the power components to handle this is cost prohibitive. furthermore, the controller cannot do anything to protect against this. turning on the boost switch makes the issue worse. there are two primary ways to solve this issue: 1. startup bypass rectifier a rectifier can be added from the input voltage to the output voltage (figure 10). this bypasses the inductor and diverts the startup current directly to the bulk capacitor. the bulk capacitor is then charged to the peak ac line voltage without resonant overshoot and without excessive inductor current. after startup, d bypass is reverse biased and does not interfere with the boost converter. 2. external inrush current limiting resistor an ntc (negative temperature coefficient) thermistor in series with the boost inductor can limit the inrush current (figure 11). the resistance value drops from a few ohms to a few milliohms as the device is heated by the i 2 r power dissipation. alternatively, this ntc can be placed in series with the boost diode. this improves the active ef ficiency as the resistor only conducts the output current instead of the input current. however, an ntc resistor may not be able to adequately protect the inductor and bulk capacitor against inrush current during a brief interruption of the mains, such as during line drop out and recovery. figure 10. use a second diode to route the inrush current away from the inductor ncp1607 + vac v in v out d bypass figure 11. use an ntc to limit the inrush current through the inductor ncp1607 + vac v in v out ntc
and8353/d http://onsemi.com 9 design step 9: develop the compensation network as stated earlier, due to the natural output voltage ripple, the bandwidth of the pfc feedback loop is generally kept below 20 hz. for a simple type 1 compensation network, only a capacitor is placed between fb and control. the gain, g(s), of the feedback network is then given by: (eq. 27) g(s) 1 s r out1 c comp therefore, the capacitor necessary to attenuate the bulk voltage ripple is given by: (eq. 28) c comp 10 g 20 4 f line r out1 where g is the attenuation level in db (commonly 60 db) and f line is the minimum ac line frequency (47 hz). figure 12. gain and phase for a type 1 feedback network 100 10 1 gain (db) phase shift ( ) 150 120 90 60 30 0 f (hz) gain (10 db/div) phase shift (deg) as shown in figure 12, a type 1 compensation network provides no phase boost to improve stability. for resistive loads, this may be sufficient (figure 13). but for constant power loads, such as smps stages, the phase margin is reduced (figure 14). phase gain phase gain phase margin = 30 100 w, 115 vac c comp = 1.1 f 40 32 24 16 8 0 ? 40 ? 32 ? 24 ? 16 ? 8 90 80 70 60 50 40 30 20 10 0 ? 10 100 10 1 mag [b/a] (db) phase [b/a] (deg) 100 w, 115 vac c comp = 1.1 f 40 32 24 16 8 0 ? 40 ? 32 ? 24 ? 16 ? 8 90 80 70 60 50 40 30 20 10 0 ? 10 100 10 1 mag [b/a] (db) phase [b/a] (deg) figure 13. boost demo board with a resistive load. phase margin = 30 deg. figure 14. boost demo board with a constant power load . phase margin is reduced to 17 deg. phase margin = 17 f(hz) f(hz) if greater system stability is required, then a type 2 compensation network is implemented. in this setup, a resistor and capacitor are placed in parallel with c comp (figure 15). fb control + ? e/a + v control r out2 r out1 c comp v out c comp1 r comp1 figure 15. type 2 compensation network v ref r fb
and8353/d http://onsemi.com 10 the transfer function for the type 2 error amplifier is now: g(s) 1 s r comp1 c comp1 s r out1 (c comp c comp1 ) 1 s r comp1 c comp c comp1 c comp c comp1 (eq. 29) this gives a pole at 0 hz, a zero at f z (eq 30), and another pole at f p (eq 31). f z 1 2 r comp1 c comp1 (eq. 30) f p f z c comp c comp1 c comp (eq. 31) phase gain figure 16. representative gain and phase for a type 2 feedback network. note the phase boost 100 10 1 gain (db) phase shift ( ) 150 120 90 60 30 0 f (hz) gain (10 db/div) phase shift (deg) 100 w, 265 vac c comp = 0.01 f c comp1 = 0.39 f r comp2 = 54.9 k r out1 = 4.0 m figure 17. improved stability with a type 2 compensation network. phase margin = 50 deg. f (hz) ? 50 0 50 100 150 200 ? 30 ? 20 ? 10 0 10 20 30 40 50 1 10 100 magnitude (db) phase shift (deg) the poor stability observed with the type 1 compensation in figure 14 improved (with the same total compensation capacitance) to figure 17. the phase margin and cross over frequency will change with the line voltage. therefore, it is critical that any design has the gain ? phase measured under all operating conditions. this is accomplished with a simple setup (figure 18) and a network analyzer.
and8353/d http://onsemi.com 11 figure 18. gain ? phase measurement setup for boost pfc pre ? converters + ac line emi filter 1 4 3 2 8 5 6 7 fb control ct cs gnd zcd drv + c bulk load v out r s c in r zcd r out1 r out2 v cc ct v cc isolator network analyzer ch a isolation probe ch b isolation probe 1 k l boost simple improvements for additional thd reduction the ncp1607, with its constant on time architecture, provides a good deal of flexibility in optimizing each design. if further power factor performance is necessary, consider the following design guidelines. 1. improve the thd/pf at full load by increasing the on time at the zero crossing: one issue with crm control is that at the zero crossing of the ac line, the voltage is not large enough to significantly charge the boost inductor during the fixed on time. little energy is processed and some ?zero crossover distortion? (figure 19) is produced. figure 19. zero crossover distortion v in (50 v/div) i in (500 ma/div) this raises the thd and lowers the lowers the pf of the pre ? converter. to meet iec1000 requirements, this is generally not an issue, as the ncp1607 delivers more than an ample reduction in current distortion. if improved thd or pf is required, then this zero crossover distortion can be reduced. the key is to increase the on time when the input voltage is low. this allows more time for the inductor to charge up and reduces the voltage level at which the distortion begins. fortunately, such a method is easy to implement on the ncp1607. if a resistor is connected from pin 3 (ct) to the input voltage, then a current proportional to the instantaneous line voltage is injected into ct (figure 20). this current is higher at the peak of the line and has nearly no effect at low input voltages.
and8353/d http://onsemi.com 12 figure 20. add r ctup to modify the on time and reduce the zero crossing distortion + ac line c in r ctup v in ct i v in r ctup v dd drv i charge + - t on pwm v eal v control ct l boost
and8353/d http://onsemi.com 13 the ct capacitor is increased in size so that the on time is longer near the zero crossing (figure 21). this also reduces the frequency variation over the ac line cycle. the tradeoff to this approach is the increased no load power dissipation created by r ctup . the designer must balance the desired thd and pf performance with the no load power dissipation requirements. figure 21. on time and switching frequency with and without r ctup vac(t) t on f sw with r ctup no r ctup with r ctup no r ctup time the effect of this resistor on thd and power factor is illustrated in figure 22. figure 22. effect of rctup on full load (100 w) thd vac (v rms ) thd (%) rctup = 1.5 m rctup = open 0 5 10 15 20 25 85 115 145 175 205 235 265 2. improve the thd/pf at light load or high line: if the required on time at light load or high line is less than the minimum on time, then the controller delivers too much power. this causes the control voltage to fall to its lowest level (v eal ). the controller then disables the drive (static ovp) to prevent the output voltage from rising too high. once the output drops lower, the control voltage rises and the cycle repeats. this adds to the distortion of the input current and output voltage ripple. there are two solutions to improve thd/pf at light load or high line: 1. properly size the ct capacitor. as mentioned above, the capacitor must be large enough to deliver the required on time at full load and low line. however, sizing it too large means that the range of control levels at light load or high line is reduced. 2. compensate for propagation delays. if optimizing the ct capacitor does not achieve the desired performance, then it may be necessary to compensate for the pwm propagation delay. when the ct voltage exceeds the v control setpoint, the pwm comparator sends a signal to end the on time of the driver (figure 23).
and8353/d http://onsemi.com 14 figure 23. block diagram of the propagation delay components ct v dd drv i charge + - pwm v eal v control control v ct(off) driver r s drv r drv v gate i switch ct r ct however, there is a delay before the mosfet fully turns off. this delay is created by the propagation delay of the pwm comparator and the time to bring the mosfet?s gate voltage to zero (figure 24). figure 24. driver turn off propagation delay v gate i switch c t c t(off) t pwm t gate t delay the total delay, t delay , is summarized in eq 32: t delay t pwm t gate (eq. 32) this delay adds to the effective on time of the controller. if a resistor (r ct ) is inserted in series with the ct capacitor, then the total on time is reduced by: t ct v rct i rct ct r ct therefore, to compensate for the propagation delay, r ct is calculated using equation 33: r ct t delay ct (eq. 33) the ncp1607 datasheet gives a typical t pwm of 100 ns. the t gate delay is a function of the mosfet?s gate charge and the resistor ?r drv .? for this demo board, the gate delay is measured at about 150 ns. a value of r ct = 300 is sufficient to compensate for the propagation delays. this improves pf and thd. at light load and high line (figure 25). figure 25. effect of rct on light load thd at 265 vac / 50 hz (rctup = open) p out (w) thd (%) rct = 300 rct = 0 0 10 20 30 40 50 60 70 25 30 35 40 45 50
and8353/d http://onsemi.com 15 design results the completed demo board schematic using the ncp1607 is shown in figure 26. figure 26. 100 w pfc pre ? converter using the ncp1607 c3 d1 + + u1 ncp1607 5 zcd 3 ct 6 gnd 4 cs 8 vcc 7 drv 1 fb 2 control j3 j1 l2 f1 c2 q1 bridge t ntc j2 l1 r1 c1 r start1 r start2 l boost d boost cv cc d aux dv cc r zcd cv cc2 d drv r drv c zcd r ctup2 r ctup1 r o1a r o1b c bulk r out2b r out2a c in c comp1 r comp2 c comp c t1 c t2 c cs r cs r s3 r s2 r s1 r ct the bill of materials (bom) and layout drawings are shown in appendix 1 and 2, respectively. this pre ? converter exhibits excellent thd (figures 27 and 28), pf (figure 29), and efficiency (figure 30).
and8353/d http://onsemi.com 16 figure 27. thd vs. input voltage at full load and 50% load figure 28. individual harmonic current at 115 vac and 230 vac vac (v rms )n th harmonic thd (%) pf p out = 100 w p out = 50 w vac (v rms ) efficiency (%) 0 2 4 6 8 10 12 14 16 18 20 85 115 145 175 205 235 265 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1357911131517192123252729313335373 9 115 vac 230 vac 115 vac limit 230 vac limit figure 29. pf vs. input voltage at full load and 50% load vac (v rms ) harmonic current (a) figure 30. efficiency vs. input voltage at full load and 50% load 0.9 0.92 0.94 0.96 0.98 1 85 115 145 175 205 235 265 p out = 100 w p out = 50 w 90 91 92 93 94 95 96 85 115 145 175 205 235 2 6 p out = 100 w p out = 50 w the input current and resultant output voltage ripple is shown in figure 31. the overvoltage protection scheme can be observed by starting up the pre ? converter with a light load on the output (figure 32). the ovp activates at about 440 v and restarts at about 410 v. figure 31. full load input current at 115 vac/60 hz figure 32. startup transient showing ovp activation and recovery v in (100 v/div) v out ripple (10 v/div) i in (1 a/div) ovp activated at 440 v ovp recovers at 410 v ncp1607 starts up here v in (100 v/div) v out (100 v/div) v cc (5 v/div) fpp jumper this demo board is equipped with a jumper between pin 1 of the controller and the feedback network to demonstrate the fpp feature of the ncp1607. if the jumper is removed prior to applying input power, the drive is disabled (figures
and8353/d http://onsemi.com 17 33, 34). if the jumper is removed at any time during operation, the drive is disabled within 1 ms (figures 35, 36). this jumper is for fpp demonstration only and is not required in the end application. figure 33. startup with jumper removed at 265 vac/50 hz, i out = 0 ma, v cc = 13 v, and t j = ? 40 c figure 34. startup with jumper removed at 265 vac/50 hz, i out = 250 ma, v cc = 20 v, and t j = ? 40 c figure 35. removing jumper during operation at 265 vac/50 hz, i out = 250 ma, v cc = 20 v, and t j = ? 40 c figure 36. removing jumper during operation at 265 vac/50 hz, i out = 0 ma, v cc = 13 v, and t j = ? 40 c v out (100 v/div) v cc (10 v/div) drv (10 v/div) i out (200 ma/div) i out (200 ma/div) drv (10 v/div) v cc (10 v/div) v out (100 v/div) i out (200 ma/div) drv (10 v/div) v cc (10 v/div) v out (100 v/div) v out (100 v/div) v cc (10 v/div) drv (10 v/div) i out (200 ma/div)
and8353/d http://onsemi.com 18 this demo board can be configured in a variety of ways to optimize performance. table 2 shows results of a few of these configurations. table 2. summary of key parameters for different variations of the demo board. rctup ct shutdown (v zcd = 0 v) pdiss @ 265 vac efficiency @ 100 w thd @ 100 w 115 vac 60 hz 230 vac 50 hz 115 vac 60 hz 230 vac 50 hz open 1.5 nf 225 mw 92.5% 94.6% 9.5% 16.7% 1.5 meg 1.8 nf 295 mw 92.5% 94.4% 4.9% 8.9% safety concerns since the fpp feature is only intended to protect the circuit in the case of a floating fb pin, care must be taken when removing the jumper. do not attach any wires to the jumper pins with the jumper removed. doing so injects noise into the fb pin and prevents the correct operation of fpp thus causing maximum power to be delivered to the output. this can cause c bulk to vent. always wear pr oper eye protection when the jumper is removed. the jumper is located next to several high-voltage components. do not remove the jumper during operation with bare fingers or non-insulated metal tools. layout considerations as with many switching power supplies, careful consideration must be given to the placement of critical components during layout. noise from the high peak currents of the main power switch are easily coupled into sensitive inputs of the ncp1607. to reduce this noise, be sure to follow these guidelines: 1. locate critical components as physically close to the controller as possible with the following priority: a. ct capacitor b. v cc decoupling capacitor c. other compensation components 2. minimize the length of all signal traces. 3. locate r s adjacent to the source pin of q1. 4. locate the ground connections for c in , bridge, r s , and c bulk as close together as possible. 5. add decoupling capacitors to the zcd and cs pin if needed. a. if a capacitor is added to these pins, r zcd and r cs may need to be adjusted to ensure proper timing. d. although the demo board does not require c zcd and c cs , it contains unpopulated footprints for both so that the user may add them if needed.
and8353/d http://onsemi.com 19 appendix 1: bill of materials (bom) designator qty description value tolerance foot ? print manufacturer manufacturer part number substitution allowed pb ? free u1 1 ncp1607 ncp1607 ? soic ? 8 on semiconductor ncp1607bdr2g no yes d1 1 diode, general purpose 100 v ? sod123 on semiconductor mmsd4148t1g no yes daux 1 diode, zener 18 v ? sod123 on semiconductor mmsz4705t1g no yes dboost 1 diode, ultrafast 4 a, 600 v ? axial on semiconductor mur460rlg no yes bridge 1 diode, bridge rectifier 4a, 600 v ? kbl vishay kbl06 ? e4/51 yes yes dvcc, ddrv 2 diode, general purpose open ? sod123 ? ? ? ? f1 1 fuse, smd 2 a, 600 v ? smd littelfuse 0461002.er yes yes lboost 1 inductor, boost, nboost:nzc d = 10:1 400 h, 10:1 ? custom coilcraft fa2890 ? cl no yes l1 1 inductor, radial 180 uh 10% through hole coilcraft pcv ? 2 ? 184 ? 05l no yes l2 1 inductor, common ? m ode choke 4.7 mh, 2.7 a ? through hole panasonic elf ? 20n027a yes yes q1 1 mosfet, n ? channel 11.6 a, 560 v ? to ? 220 infineon spp12n50c3 yes yes ntc 1 thermistor, inrush current limiter 4.7 20% radial epcos b57238s479m yes yes rcomp1 1 resistor, smd 54.9 k 1% 1206 yageo rc1206fr ? 0754k9l yes yes r1 1 resistor, smd 100 1% 1206 yageo rc1206fr ? 07100rl yes yes rct 1 resistor, smd 0 1% 1206 yageo rc1206fr ? 070rl yes yes rdrv 1 resistor, smd 10.0 1% 1206 yageo rc1206fr ? 0710rl yes yes rout2a 1 resistor, smd 25.5 k 1% 1206 yageo rc1206fr ? 0725k5l yes yes ro1a,ro1b 2 resistor, smd 2.00 m 1% 1206 yageo rc1206fr ? 072ml yes yes rs1 1 resistor, smd 0.100 , 1 w 1% 2512 koa sr733atter100f yes yes rs2,rs3 2 resistor, smd open ? 2512 ? ? ? ? rout2b 1 resistor, smd open ? 1206 ? ? ? ? rcs 1 resistor, 1/4 w axial 510 5% axial yageo cfr ? 25jb ? 510r yes yes rctup1, rctup2 2 resistor, 1/4 w axial 750 k 5% axial yageo cfr ? 25jb ? 750k yes yes rzcd 1 resistor, 1/4 w axial 51 k 5% axial yageo cfr ? 25jb ? 51k yes yes rstart1, rstart2 2 resistor, 1/4 w axial 330 k 5% axial yageo cfr ? 25jb ? 330k yes yes c1,c2 2 x capacitor 0.47u 20% radial epcos b32923c3474m yes yes cin 1 x capacitor 0.1u 20% radial epcos b32921a2104m yes yes cvcc 1 capacitor, electrolytic 47 uf, 25 v 20% radial panasonic eeu ? fc1e470 yes yes
and8353/d http://onsemi.com 20 appendix 1: bill of materials (bom) designator pb ? free substitution allowed manufacturer part number manufacturer foot ? print tolerance value description qty cbulk 1 capacitor, electrolytic 68 f, 450 v 20% radial ncc ekxg451ell680mm n3s yes yes cvcc2,ccomp 2 capacitor, ceramic, smd 0.1 f, 25 v 10% 1206 vishay vj1206y104kxx yes yes ccomp1 1 capacitor, ceramic, smd 0.39 f, 25 v 10% 1206 vishay vj1206y394kxx yes yes ct1 1 capacitor, ceramic, smd 1.5 nf, 25 v 10% 1206 vishay vj1206y152kxx yes yes ct2 1 capacitor, ceramic, smd 330 pf, 25 v 10% 1206 vishay vj1206y331kxx yes yes c3 1 capacitor, ceramic, smd 22 nf, 25 v 10% 1206 vishay vj1206y223kxx yes yes czcd,ccs 2 capacitor, ceramic, smd open ? 1206 ? ? ? ? j1 1 header 1 row of 3, 1 row of 2 ? 2.54 mm 3m 929400 ? 01 ? 36 yes yes j2,j3 2 connector, 156 mil 3 pin ? ? 156 mil molex 26 ? 60 ? 4030 yes yes mechanical 1 jumper, shorting ? ? ? 3m 929955 ? 06 yes yes mechanical 1 heatsink ? ? to220 aavid 590302b03600 yes yes mechanical 1 screw 4 ? 40 1/4? screw ? ? building fasteners pmsss 440 0025 ph yes yes mechanical 1 nut 4 ? 40 screw nut ? ? building fasteners hnss440 yes yes mechanical 1 nylon washer shoulder washer #4 ? ? keystone 3049 yes yes mechanical 1 to220 thermal pad 9 mil ? ? wakefield 173 ? 9 ? 240p yes yes mechanical 4 standoffs hex 4 ? 40, nylon 0.75? ? ? keystone 4804k yes yes mechanical 4 nylon nut hex 4 ? 40 ? ? building fasteners ny hn 440 yes yes
and8353/d http://onsemi.com 21 appendix 2: layout drawings figure 37. bottom view of 100 w board layout figure 38. top view of 100 w board layout
and8353/d http://onsemi.com 22 appendix 3: summary of boost equations for the ncp1607 rms input current i ac p out v ac (the efficiency of only the boost pfc stage) is generally in the range of 90 ? 95% maximum inductor peak current i pk(max) 2 2 p out vac ll where vac ll is the minimum line in- put voltage. i pk(max) occurs at the lowest line voltage. inductor value l 2 vac 2 v out 2 vac v out vac i pk(max) f sw(min) f sw(min) is the minimum desired switching frequency. the maximum l must be calculated at low line and high line. maximum on time t on(max) 2 l p out vac ll 2 the maximum on time occurs at the lowest line voltage and maximum output power. off time t off t on v out vac sin( ) 2 1 the off time is greatest at the peak of the ac line voltage and ap- proaches zero at the ac line zero crossings. theta ( ) represents the angle of the ac line voltage. frequency f sw vac 2 2 l p out 1 vac | sin | 2 v out pin 3 capacitor ct
2 p out l i charge vac 2 v ctmax i chart and v ctmax are given in the ncp1607 specification table. boost turns to zcd turns ratio n b :n zcd v out vac hl 2 v zcdh where v achl is the maximum line input voltage. the turns ratio must be low enough so as to trigger the zcd comparators at high line. resistor from zcd wind- ing to the zcd pin (pin 5) r zcd
vac hl 2 i cl(neg) (n b :n zcd ) r zcd must be large enough so that the shutdown comparator is not in- advertently activated. boost output voltage v out v ref r out1 r eq r eq r eq r out2 r fb r out2 r fb maximum v out voltage prior to ovp activation and the necessary r out1 and r out2 . v out(ovp) v out r out1 i ovp r out1 v out(ovp) v out i ovp r eq r out1 v ref v out v ref r out2 r eq r fb r fb r eq i ovp is given in the ncp1607 spe- cification table. minimum output voltage necessary to exit under- voltage protection (uvp) v out(uvp) r out1 r eq r eq v uvp v uvp is given in the ncp1607 spe- cification table. bulk cap ripple v ripple(pk ? pk) p out c bulk 2 f line v out use f line = 47 hz for worst case at universal lines. the ripple must not exceed the ovp level for v out . inductor rms current i l(rms) 2 p out 3 vac ll boost diode rms current i d(rms)max 4 3 2 2 p out vac ll v out
and8353/d http://onsemi.com 23 appendix 3: summary of boost equations for the ncp1607 mosfet rms current i m(rms)max 2 3 p out vac ll 2 1 8 2 vac ll 3 v out mosfet sense resistor r s v cs(limit) i pk(max) p rs i m(rms) 2 r s v cs(limit) is given in the ncp1607 specification table. bulk capacitor rms current i c(rms)max 32 2 p out 2 9 vac ll v out 2 (i load(rms) ) 2 c comp for type 1 c comp 10 g 20 4 f line r out1 g is the desired attenuation in decibels (db). typically it is 60 db. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 and8353/d the product described herein (ncp1607), may be covered by the following u.s. patents: 5,073,850 and 6,362,067. there may be oth er patents pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative

▲Up To Search▲

Price & Availability of AND8353D

	To Download AND8353D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .